This invention relates generally to semiconductor devices, and more specifically to integrated circuit devices having regions of low capacitance.
Semiconductor device technology continues to scale transistors to smaller and smaller dimensions to provide increased functionality and improved high frequency performance. By way of example, wireless communication devices often use integrated circuits that include high-density digital signal processing functions on a single chip together with analog circuits operating at frequencies greater than five gigahertz (GHz).
Although transistor devices are more easily scalable, other integrated circuit components are not as readily scalable. Such components include passive devices that often have relatively high parasitic substrate capacitances, which can limit the overall frequency performance of an integrated circuit. Inductors are an example of passive components that are not easily reduced in size without reducing their quality factor (Q) or inductance to unacceptable levels. Additionally, bonding pads are not readily scalable because manufacturers must attach bonding wires to the bonding pads.
Semiconductor manufacturers have attempted several techniques to reduce parasitic capacitance effects associated with passive components. One such technique is to form the passive components over a low permittivity material. However, such materials in use today are limited by film thickness, which is often too thin to provide a sufficient reduction in capacitance, or cost with materials such as silicon on insulator. Another approach is to form the passive components over a thick dielectric film that includes air gaps or voids that reduce the overall permittivity of the dielectric film. However, such films have been found to produce significant stresses on semiconductor devices, which degrade device performance and reliability. Also, the air gaps act as sources of contamination because they trap moisture and other chemicals during wafer processing. The trapped contaminants then outgas during later processing and impact device yields and reliability. Other approaches reduce the stress by producing fewer voids or voids with limited volume, which has a correspondingly limited effect on parasitic capacitance.
Accordingly, a need exists for a low capacitance structure and method of a making a semiconductor device that maintains a low cost while reducing die stresses. It would be a further advantage for such structures and methods to avoid air gaps and their associated contamination problems. It would be a still further advantage for such structures and methods to be easily integrated into standard integrated circuit process flows.